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High Density Coreless ETS BT IC Substrate for Ultra-Thin FC-CSP and SiP
High Density Coreless ETS BT IC Substrate for Ultra-Thin FC-CSP and SiP
Specifications
Payment Terms :
L/C,D/A,D/P,T/T
Price :
negotiate
Line/Space Capability :
10/10 μm to 30/30 μm (SAP/MSAP)
Brand Name :
Jiaqing Circuit
Delivery Time :
15-30 Days
Glass Transition Temperature :
180°C – 225°C (DSC)
Place of Origin :
China
Layer Count :
2 – 12 layers
Via Diameter :
50 – 100 μm
Surface Finish :
ENIG, ENEPIG, OSP
Core Thickness :
40 – 200 μm
Certification :
ISO9001
Material :
BT (Bismaleimide Triazine) resin
Description

Coreless ETS (Embedded Trace Substrate) BT IC substrate eliminates the thick glass-cloth reinforced core to achieve ultra-thin profiles (as thin as 0.13 mm for 2-6 layer structures) and superior warpage control. By embedding the outermost circuit pattern directly into the BT insulating material, ETS technology enables fine line/space down to 12/12 μm (sample) and 12/18 μm (mSAP production). The coreless construction reduces overall package height for FC-CSP applications (3*3 mm to 19*19 mm) with bump pitches ≥0.15 mm. Available in 2-8 layer configurations, these substrates are ideal for ultra-thin mobile devices, wearable electronics, and high-density SiP modules where thickness and warpage are critical constraints.

Applications & Key Advantages by Category
Ultra-Thin Mobile Devices

Coreless construction (as thin as 0.13 mm) enables thinner smartphones, tablets, and wearables without sacrificing interconnect density.

Wearable Electronics

The ultra-thin profile and reduced warpage make ETS BT substrates ideal for smartwatches, hearables, and health monitoring devices.

SiP (System-in-Package) Modules

Coreless technology supports multi-chip integration in compact form factors, essential for RF front-end modules and sensor hubs.

High-Density FC-CSP

Fine line/space (12/18 μm) and bump pitch ≥0.15 mm enable high I/O count in compact package sizes (3*3 mm to 19*19 mm).

Warpage-Sensitive Applications

The coreless structure significantly reduces package warpage compared to conventional substrates, critical for large-die flip-chip assemblies and assembly yield optimization.

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High Density Coreless ETS BT IC Substrate for Ultra-Thin FC-CSP and SiP

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Product Detail
Payment Terms :
L/C,D/A,D/P,T/T
Price :
negotiate
Line/Space Capability :
10/10 μm to 30/30 μm (SAP/MSAP)
Brand Name :
Jiaqing Circuit
Delivery Time :
15-30 Days
Glass Transition Temperature :
180°C – 225°C (DSC)
Contact Supplier
High Density Coreless ETS BT IC Substrate for Ultra-Thin FC-CSP and SiP

Shenzhen Jiaqing Circuit Co., Ltd.

Verified Supplier
1 Years
shenzhen
Since 2012
Business Type :
Manufacturer
Main Products :
IC Substrate Board, PCBA, Standard PCB
Total Annual :
20000000-50000000
Employee Number :
201~300
Certification Level :
Verified Supplier
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