MPU EZ-PD™ CCG3PA Consumer USB Type-C Portcontroller Chip CYPD3171-24LQXQT

The Cortex®-M0 CPU in EZ-PD™ CCG3PA is part of the 32-bit MCU subsystem, which is optimized for low-poweroperation with extensive clock gating.The CPU also includes a serial wire debug (SWD) interface for programming and debugging. The debug configuration used for EZ-PD™ CCG3PA has four breakpoint (address) comparators and two watchpoint (data) comparators.1.1.2 FlashThe EZ-PD™ CCG3PA device has a flash module with one bank of 64-KB flash, a flash accelerator, tightly coupledto the CPU to improve average access times from the flash block.1.1.3 SROMA supervisory ROM that contains boot and configuration routines is provided.1.2 USB PD subsystem (SS)The USB PD subsystem provides the interface to the Type-C USB port. This subsystem comprises a current senseamplifier, a high-voltage regulator, OVP, OCP, and supply switch blocks. This subsystem also includes all ESDrequired and supported on the Type-C port.1.2.1 USB PD physical layerThe USB PD physical layer consists of a transmitter and receiver that communicate BMC-encoded data over theCC channel based on the PD 3.1 standard. All communication is half-duplex. The physical layer or PHYimplements collision avoidance to minimize communication errors on the channel.The USBPD block includes all termination resistors (RP and RD) and their switches as required by the USB PD spec.RP and RD resistors are required to implement connection detection, plug orientation detection, and for establishing USB DFP/UFP roles. The RP resistor is implemented as a current source.According to the USB Type-C spec, a Type-C controller such as CCG3PA must present certain termination resistorsdepending on its role in its unpowered state. The sink role in a power bank application requires RD resistors tobe present on the CC pins whereas the DFP role, as in a power adapter, requires both CC lines to be open. To beflexible for such applications, CCG3PA includes the resistors required in the unpowered state on separate padsor pins. The dead battery RD resistors are available on separate pads. The dead battery RD is implemented as abond option on parts for Power Bank applications. In these parts, each CC pin is bonded out together with itscorresponding dead battery RD resistor. On part numbers for the DFP application, the CC pins are not bondedwith the dead battery RD.1.2.2 Analog-to-digital converter (ADC)An 8-bit SAR ADC is available for general-purpose A-D conversion applications in the chip. This ADC can beaccessed from all GPIOs and the DP/DM pins through an on-chip analog mux. CCG3PA contains two instances ofthe ADC. The voltage reference for the ADCs is generated either from the VDDD supply or from internal bandgap.When sensing the GPIO pin voltage with an ADC, the pin voltage cannot exceed the VDDIO supply value.1.2.3 Charger detectionThe two charger detection blocks connected to the two pairs of DP/DM pins allow CCG3PA to emulate legacybattery chargers conforming to BC 1.2, and the following proprietary charger specifications: Apple, Qualcomm’sQuickCharge 4.0, and Samsung AFC.1.2.4 VBUS overcurrent and overvoltage protectionThe CCG3PA chip has an integrated hardware block for VBUS overvoltage protection (OVP)/overcurrentprotection (OCP) with configurable thresholds and response times on the Type C port.

Packaging and transportation instructions

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Customers can choose from cartons, wooden cases and wooden pallets according to their own requirements.

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