HACC102T50V601 Deep-Trench MOS Capacitor — 1000 pF 50 V High-Density Single Layer Chip with Bias-Stable Dielectric

The HACC102T50V601 is a 1000 pF ±10% single-layer MOS capacitor rated at 50 V DC, built on a 3D deep-trench silicon architecture in which deep trenches etched into the silicon substrate multiply the effective electrode area within the same die footprint. The capacitor delivers 1000 pF in a 0.50 mm × 0.50 mm die; for reference, planar 1000 pF MOS capacitors in this series use 0.75 mm-class die, so the trench design provides roughly twice the capacitance per unit area for space-constrained hybrid modules. A MOS capacitor is a single-layer capacitor formed by a metal-oxide-semiconductor structure (thermal silicon dioxide on a conductive silicon substrate), valued for low ESL, stable capacitance and high insulation resistance.

3D Deep-Trench Architecture for Ultra-High Volumetric Efficiency

• Etched trench electrodes increase effective plate area per unit footprint, achieving 1000 pF at 50 V in a 0.50 × 0.50 mm outline with a 0.18 mm profile;
• Roughly 2× area efficiency versus planar 1000 pF MOS capacitors of this series, freeing carrier area for additional die in hybrid microcircuits;
• Full bottom-side metallization preserves maximum thermal contact and low-inductance current path despite the 3D structure;
• Custom trench layouts, die sizes and aspect ratios (up to 4:1) are available for customer-specific footprints.

Electrical Characteristics (typical, 25°C unless noted)

Typical Applications

Compact DC bias decoupling and bypass in hybrid microcircuits and multi-chip modules; RF power amplifier bias networks; space-constrained microwave assemblies; filter and timing networks requiring bias-stable capacitance; high-density energy storage in pulsed circuits.